Synopsys spreads AI throughout its chip design tools

Synopsys first released an AI tool for one part of the chip design process three years ago

(Reuters) - Synopsys Inc (SNPS.O) on Wednesday rolled out new artificial intelligence tools designed to get better results faster in the various stages of designing computing chips.

Synopsys makes software that companies use to design computing chips. Modern chips have tens of billions of tiny on-off switches called transistors, and their precise arrangement on the chip has a big impact on the chip's cost and performance, so designers use software from companies like Synopsys to help.

Synopsys first released an AI tool for one part of the chip design process three years ago, and customers like Samsung Electronics Co Ltd (005930.KS) and ST Microelectronics (STM.DE) use the system.

The tools Synopsys released on Wednesday at its annual user conference in Santa Clara, California, spread much further across the chip design process. They are aimed at helping engineers hunt for bugs in their designs, test physical sample chips from manufacturing partners and, once mass production has begun, boost the proportion of defect-free chips coming off the production line.

Synopsys is in a race with Cadence Design Systems (CDNS.O), its largest competitor, to add AI to chip design software. While some of the Synopsys tools released Wednesday are catching up to Cadence, Karl Freund, principal analyst with Cambrian AI research, said Synopsys is ahead, with more than 100 chips by customers using its AI tools coming to market.

"They definitely lap Cadence, especially if you look at what's happened with physical design," Freund said. "I think they'll probably be at 1,000 (completed chip designs) by the end of the year."

Synopsys CEO Aart de Geus said the company plans to invest more in AI tools in the coming years as the semiconductor industry shifts toward what are know as chiplets - multiple chips stacked and stitched together to create larger, more complicated chips.

"When you design multiple chips that are literally sort of glued together, you don't design them in isolation," he said in an interview during the conference. "You optimize them together."